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dc.contributor.authorTZENG, EGen_US
dc.contributor.authorLEE, CYen_US
dc.date.accessioned2014-12-08T15:27:47Z-
dc.date.available2014-12-08T15:27:47Z-
dc.date.issued1995en_US
dc.identifier.isbn0-7803-2570-2en_US
dc.identifier.issn0277-674Xen_US
dc.identifier.urihttp://hdl.handle.net/11536/20030-
dc.language.isoen_USen_US
dc.titleAn efficient memory architecture for motion estimation processor designen_US
dc.typeProceedings Paperen_US
dc.identifier.journal1995 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3en_US
dc.citation.spage712en_US
dc.citation.epage715en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:A1995BD85N00179-
顯示於類別:會議論文