| 標題: | Complementary-LVTSCR ESD protection scheme for submicron CMOS IC's |
| 作者: | KER, MD WU, CY CHANG, HH CHENG, T WU, TS 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
| 公開日期: | 1995 |
| URI: | http://hdl.handle.net/11536/20031 |
| ISBN: | 0-7803-2570-2 |
| ISSN: | 0277-674X |
| 期刊: | 1995 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3 |
| 起始頁: | 833 |
| 結束頁: | 836 |
| 顯示於類別： | Conferences Paper |
- Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI / Ker, MD;Wu, CY;Chang, HH
- A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS IC's / Ker, MD;Chang, HH;Wu, CY
- Cascoded LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup danger / Ker, MD;Chang, HH
- Native-NMOS-triggered SCR With faster turn-on speed for effective ESD protection in a 0.13-mu m CMOS process / Ker, MD;Hsu, KC
- 互補式金氧半積體電路之靜電放電保護電路及低同步切換雜訊輸出驅動級之設計 / 張恆祥;Chang Hun-Hsien;吳錦川;柯明道;Jiin-Chuan Wu
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