ON THE REDUCTION OF REORDER BUFFER SIZE FOR DISCRETE FOURIER TRANSFORM PROCESSOR DESIGN

標題:	ON THE REDUCTION OF REORDER BUFFER SIZE FOR DISCRETE FOURIER TRANSFORM PROCESSOR DESIGN
作者:	SHEN, WZ TAO, YH DUNG, LR 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics
公開日期:	1994
URI:	http://hdl.handle.net/11536/20185
ISBN:	0-7803-1915-X
期刊:	1994 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 4: VLSI
起始頁:	D171
結束頁:	D174
Appears in Collections:	Conferences Paper