AN ALGORITHMIC ANALOG-TO-DIGITAL CONVERTER WITH LOW RATIO-SENSITIVITY AND GAIN-SENSITIVITY AND 4N-CLOCK CONVERSION CYCLE

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	CHIN, SY	en_US
dc.contributor.author	WU, CY	en_US
dc.date.accessioned	2014-12-08T15:27:55Z	-
dc.date.available	2014-12-08T15:27:55Z	-
dc.date.issued	1994	en_US
dc.identifier.isbn	0-7803-1915-X	en_US
dc.identifier.uri	http://hdl.handle.net/11536/20188	-
dc.language.iso	en_US	en_US
dc.title	AN ALGORITHMIC ANALOG-TO-DIGITAL CONVERTER WITH LOW RATIO-SENSITIVITY AND GAIN-SENSITIVITY AND 4N-CLOCK CONVERSION CYCLE	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	1994 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 5: LINEAR CIRCUITS AND SYSTEMS (LCS) - ANALOG SIGNAL PROCESSING (ASP)	en_US
dc.citation.spage	E325	en_US
dc.citation.epage	E328	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:A1994BB78A00019	-
顯示於類別：	會議論文