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dc.contributor.authorYu, Chien-Yingen_US
dc.contributor.authorChung, Ching-Cheen_US
dc.contributor.authorYu, Chia-Jungen_US
dc.contributor.authorLee, Chen-Yien_US
dc.date.accessioned2014-12-08T15:28:14Z-
dc.date.available2014-12-08T15:28:14Z-
dc.date.issued2012-10-01en_US
dc.identifier.issn1549-7747en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCSII.2012.2213357en_US
dc.identifier.urihttp://hdl.handle.net/11536/20452-
dc.description.abstractThis brief presents a low-power small-area digitally controlled oscillator (DCO). The coarse-fine architecture with binary-weighted delay stages is applied for the delay range and resolution optimization. The coarse-tuning stage of the DCO uses the interlaced hysteresis delay cell, which is power and area efficient, as compared with conventional delay cells. The glitch protection synchronous circuit makes the DCO easily controllable without generating glitches. A demonstrative all-digital phase-locked loop using the DCO is fabricated in a 90-nm CMOS process with an active area of 0.0086 mm(2). The measured output frequency range is 180-530 MHz at the supply of 1 V. The power consumption are 466 and 357 mu W at 480- and 200-MHz output, respectively.en_US
dc.language.isoen_USen_US
dc.subjectAll-digital phase-locked loop (ADPLL)en_US
dc.subjectdigitally controlled oscillator (DCO)en_US
dc.subjectinterlaced hysteresis delay cell (IHDC)en_US
dc.subjectlow poweren_US
dc.titleA Low-Power DCO Using Interlaced Hysteresis Delay Cellsen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCSII.2012.2213357en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFSen_US
dc.citation.volume59en_US
dc.citation.issue10en_US
dc.citation.spage673en_US
dc.citation.epage677en_US
dc.contributor.department電機工程學系zh_TW
dc.contributor.departmentDepartment of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000310138700013-
dc.citation.woscount2-
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