完整後設資料紀錄
DC 欄位語言
dc.contributor.authorLai, Ming-Huien_US
dc.contributor.authorWu, YewChung Sermonen_US
dc.contributor.authorTung, Teng-Fuen_US
dc.contributor.authorWu, Hung-Yuen_US
dc.date.accessioned2014-12-08T15:29:05Z-
dc.date.available2014-12-08T15:29:05Z-
dc.date.issued2010en_US
dc.identifier.isbn978-1-60768-141-0en_US
dc.identifier.issn1938-5862en_US
dc.identifier.urihttp://hdl.handle.net/11536/20987-
dc.identifier.urihttp://dx.doi.org/10.1149/1.3375628en_US
dc.description.abstractA cap oxide layer was employed to substantially decrease nickel residues and passivate the trap states of the devices. F+ implantation was used to drive Ni in alpha-Si layer to induce crystallization (DIC) process with cap oxide to reduce Ni concentration and minimize the trap-state density. As a result, DIC-TFT with cap oxide exhibit higher field-effect mobility, lower subthreshold slope, lower threshold voltage, higher on/off current ratio, and lower trap-state density (N-t) compared with conventional MIC TFTs.en_US
dc.language.isoen_USen_US
dc.titleImproved Performance of MIC Poly-Si TFTs Using Driven-in Nickel Induced Crystallization (DIC) with Cap SiO2 by F implantationen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1149/1.3375628en_US
dc.identifier.journalADVANCED GATE STACK, SOURCE/DRAIN, AND CHANNEL ENGINEERING FOR SI-BASED CMOS 6: NEW MATERIALS, PROCESSES, AND EQUIPMENTen_US
dc.citation.volume28en_US
dc.citation.issue1en_US
dc.citation.spage405en_US
dc.citation.epage407en_US
dc.contributor.department材料科學與工程學系zh_TW
dc.contributor.departmentDepartment of Materials Science and Engineeringen_US
dc.identifier.wosnumberWOS:000313489900046-
顯示於類別:會議論文


文件中的檔案:

  1. 000313489900046.pdf

若為 zip 檔案,請下載檔案解壓縮後,用瀏覽器開啟資料夾中的 index.html 瀏覽全文。