完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | JUANG, MH | en_US |
dc.contributor.author | LIN, CT | en_US |
dc.contributor.author | CHENG, HC | en_US |
dc.date.accessioned | 2014-12-08T15:03:35Z | - |
dc.date.available | 2014-12-08T15:03:35Z | - |
dc.date.issued | 1995-01-01 | en_US |
dc.identifier.issn | 0038-1101 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/2120 | - |
dc.description.abstract | Silicided shallow p (+) n junctions formed by BF2+ implantation into thin Co films on Si substrates to a low dosage (5 x 10(14) cm(-2)) and subsequent rapid thermal annealing (RTA) or conventional furnace annealing (CFA) are used to show the impact of silicides on junction characteristics. CFA results in a lower leakage than RTA at a low bias as 5 V at high temperatures attributable to longer annealing time. All the diodes made by RTA exhibit a hard-breakdown behavior. For CFA 700 degrees C annealing, however, an anomalously poor reverse I-V behavior indicative of athermal emission is found at high bias. In addition, the 800 degrees C-formed diodes and the CFA-treated 1x10(16) cm(-2) implanted samples show good reverse characteristics even at high bias. As a result, annealing conditions should be properly chosen to reduce the impact of silicides on shallow junctions. | en_US |
dc.language.iso | en_US | en_US |
dc.title | SILICIDE-CAUSED ANOMALOUS REVERSE CURRENT-VOLTAGE CHARACTERISTICS OF COSI2 SHALLOW P(+)N JUNCTIONS | en_US |
dc.type | Article | en_US |
dc.identifier.journal | SOLID-STATE ELECTRONICS | en_US |
dc.citation.volume | 38 | en_US |
dc.citation.issue | 1 | en_US |
dc.citation.spage | 101 | en_US |
dc.citation.epage | 103 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:A1995QC42000014 | - |
dc.citation.woscount | 0 | - |
顯示於類別: | 期刊論文 |