標題: | 135-MHz 258-K Gates VLSI Design for All-Intra H.264/AVC Scalable Video Encoder |
作者: | Li, Gwo-Long Chen, Tzu-Yu Shen, Meng-Wei Wen, Meng-Hsun Chang, Tian-Sheuan 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | All-intra;scalable video coding (SVC);VLSI architecture design |
公開日期: | 1-四月-2013 |
摘要: | To satisfy the video application diversities, an extension of H.264/advanced video coding (AVC), called scalable video coding (SVC), is designed to provide multiple demanded video data via a single video encoder. However, constructed on the fundamental of H.264/AVC, the complexity of SVC is much higher than that of H.264/AVC. In this paper, a VLSI design for all-intra scalable video encoder is proposed to aim at efficient scalable video encoding. First, the memory bandwidth requirements for several encoding methods are analyzed to find out the best encoding method which can achieve best tradeoff between internal memory usage and external memory access. Afterward, an all-intra SVC encoder combined with several advanced techniques, including fast intra prediction algorithm, efficient syntax element encoding approach in context-adaptive variable-length coding, and hardware-efficient techniques, are implemented in a macroblock (MB)-level pipeline to increase data throughput. Implementation results demonstrate that our proposed SVC encoder can process more than 594-k MBs per second, which is equivalent to the summation of 60 high-definition, 1080-p, SD 480-p, and common intermediate format frames under 135-MHz working frequency. The proposed design consumes 258-K gate counts when synthesized by 90-nm CMOS technology. |
URI: | http://dx.doi.org/10.1109/TVLSI.2012.2190536 http://hdl.handle.net/11536/21354 |
ISSN: | 1063-8210 |
DOI: | 10.1109/TVLSI.2012.2190536 |
期刊: | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS |
Volume: | 21 |
Issue: | 4 |
起始頁: | 636 |
結束頁: | 647 |
顯示於類別: | 期刊論文 |