標題: | A Novel Charge-Trapping-Type Memory With Gate-All-Around Poly-Si Nanowire and HfAlO Trapping Layer |
作者: | Lee, Ko-Hui Lin, Horng-Chih Huang, Tiao-Yuan 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Charge-trap memory;endurance;gate-all-around (GAA);HfAlO;nanowire (NW);retention |
公開日期: | 1-三月-2013 |
摘要: | Hf-based charge-trapping (CT) layers, including HfO2 and HfAlO, were employed in the fabrication of a CT-type memory with gate-all-around (GAA) poly-Si nanowire channels. It is shown that the GAA configuration can greatly enhance the programming/erasing efficiency as compared with the conventional planar scheme. It is also shown that the incorporation of Al into the dielectric can further improve the retention and endurance characteristics over the counterparts with a HfO2 trapping layer. Retardation of the recrystallization of the dielectric film with Al incorporation is postulated to be responsible for these observations. |
URI: | http://dx.doi.org/10.1109/LED.2013.2237748 http://hdl.handle.net/11536/21406 |
ISSN: | 0741-3106 |
DOI: | 10.1109/LED.2013.2237748 |
期刊: | IEEE ELECTRON DEVICE LETTERS |
Volume: | 34 |
Issue: | 3 |
起始頁: | 393 |
結束頁: | 395 |
顯示於類別: | 期刊論文 |