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dc.contributor.authorYeh, Chih-Tingen_US
dc.contributor.authorKer, Ming-Douen_US
dc.date.accessioned2014-12-08T15:29:54Z-
dc.date.available2014-12-08T15:29:54Z-
dc.date.issued2013-02-01en_US
dc.identifier.issn0026-2714en_US
dc.identifier.urihttp://dx.doi.org/10.1016/j.microrel.2012.09.016en_US
dc.identifier.urihttp://hdl.handle.net/11536/21445-
dc.description.abstractA new power-rail ESD clamp circuit designed with PMOS as main ESD clamp device has been proposed and verified in a 65 nm 1.2 V CMOS process. The new proposed design with adjustable holding voltage controlled by the ESD detection circuit has better immunity against mis-trigger or transient-induced latch-on event. The layout area and the standby leakage current of this new proposed design are much superior to that of traditional RC-based power-rail ESD clamp circuit with NMOS as main ESD clamp device. (C) 2012 Elsevier Ltd. All rights reserved.en_US
dc.language.isoen_USen_US
dc.titlePMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuiten_US
dc.typeArticleen_US
dc.identifier.doi10.1016/j.microrel.2012.09.016en_US
dc.identifier.journalMICROELECTRONICS RELIABILITYen_US
dc.citation.volume53en_US
dc.citation.issue2en_US
dc.citation.spage208en_US
dc.citation.epage214en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000315614600006-
dc.citation.woscount0-
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