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dc.contributor.authorWang, Shao-Chengen_US
dc.contributor.authorLin, Geng-Cingen_US
dc.contributor.authorLin, Yi-Weien_US
dc.contributor.authorTsai, Ming-Chienen_US
dc.contributor.authorChiu, Yi-Weien_US
dc.contributor.authorJou, Shyh-Jyeen_US
dc.contributor.authorChuang, Ching-Teen_US
dc.contributor.authorLien, Nan-Chunen_US
dc.contributor.authorShih, Wei-Chiangen_US
dc.contributor.authorLee, Kuen-Dien_US
dc.contributor.authorChu, Jyun-Kaien_US
dc.date.accessioned2014-12-08T15:30:03Z-
dc.date.available2014-12-08T15:30:03Z-
dc.date.issued2012en_US
dc.identifier.isbn978-1-4577-1728-4en_US
dc.identifier.urihttp://hdl.handle.net/11536/21523-
dc.description.abstractWe present an all-digital monitor structure to measure the Write Margin (WM) with dynamic Word-Line (WL) pulse for standard CMOS 6T SRAM. Ring oscillator and frequency divider based structures are used to generate wide range WL pulses (150ps similar to 32ns) with resolution of 50ps. The bit-line voltage is then successively stepped down for dynamic Write Margin characterization under given word-line pulse width. An improved Skitter based structure is employed to measure the WL pulse width with resolution of 10 similar to 20ps. Implementation of a 256Kb test chip in UMC 55nm Standard Performance (SP) CMOS technology is described.en_US
dc.language.isoen_USen_US
dc.titleDesign and Implementation of Dynamic Word-Line Pulse Write Margin Monitor for SRAMen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2012 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS)en_US
dc.citation.spage116en_US
dc.citation.epage119en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000316598900030-
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