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dc.contributor.authorYang, Po-Jenen_US
dc.contributor.authorHuang, Po-Tsangen_US
dc.contributor.authorHwang, Weien_US
dc.date.accessioned2014-12-08T15:30:05Z-
dc.date.available2014-12-08T15:30:05Z-
dc.date.issued2012en_US
dc.identifier.isbn978-1-4673-0219-7en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/21552-
dc.description.abstractIn this paper, a substrate noise suppression technique is proposed for the power integrity of TSV 3D integrations. This substrate noise suppression technique reduces both substrate and TSV coupling noises using active substrate decouplers (ASDs) to absorb the substrate noise current. Additionally, the ASD placing is also presented to suppress noises effectively for different 3D structures. For a processor-memory stacking integration, the ground bouncing noises can be reduced by 44.1% via the noise suppression technique. The proposed substrate noise suppression technique can enhance the power integrity of TSV 3D-ICs by reducing the coupling substrate noises.en_US
dc.language.isoen_USen_US
dc.titleSubstrate Noise Suppression Technique for Power Integrity of TSV 3D Integrationen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000316903703118-
Appears in Collections:Conferences Paper