A 10-Bit 200-MS/s Digitally-Calibrated Pipelined ADC Using Switching Opamps

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DC Field	Value	Language
dc.contributor.author	Fang, Bing-Nan	en_US
dc.contributor.author	Wu, Jieh-Tsorng	en_US
dc.date.accessioned	2014-12-08T15:30:05Z	-
dc.date.available	2014-12-08T15:30:05Z	-
dc.date.issued	2012	en_US
dc.identifier.isbn	978-1-4673-0219-7	en_US
dc.identifier.issn	0271-4302	en_US
dc.identifier.uri	http://hdl.handle.net/11536/21561	-
dc.description.abstract	A 10-bit 200-MS/ s pipelined ADC was fabricated using a 90 nm CMOS technology. Switching opamps are used to save power. They are designed for high speed and fast turnon time. Digital background calibration is used to correct the conversion error caused by the low dc gain of the opamps. The ADC consumes 26 mW from a 1.1 V supply. Its measured DNL and INL are + 0.98/-0.81 LSB and + 1.4/-1.5 LSB respectively. Its measured SNDR and SFDR are 55 dB and 67.2 dB respectively. The chip active area is 0.69 mm(2).	en_US
dc.language.iso	en_US	en_US
dc.title	A 10-Bit 200-MS/s Digitally-Calibrated Pipelined ADC Using Switching Opamps	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012)	en_US
dc.citation.spage	1042	en_US
dc.citation.epage	1045	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000316903701066	-
Appears in Collections:	Conferences Paper