標題: | A CMOS 15-bit 125-MS/s time-interleaved ADC with digital background calibration |
作者: | Lee, Zwei-Mei Wang, Cheng-Yeh Wu, Jieh-Tsorng 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | analog-digital conversion;calibration;sample and hold circuits |
公開日期: | 1-十月-2007 |
摘要: | A 15-bit 125-MS/s two-channel time-interleaved pipelined ADC is fabricated in a 0.18 mu m CMOS technology, and achieves 91.9 dB SFDR, 69.9 dB SNDR for a 9.99 MHz input. This ADC incorporates a single sample-and-hold amplifier which employs a precharged circuit configuration to mitigate performance requirements for its opamp. Digital background calibration is applied to maintain the conversion linearity of each A/D channel and also correct both gain and offset mismatches between the two channels. Excluding I/O buffers, the chip occupies an area of 4.3 x 4.3 mm(2) and dissipates 909 mW from a 1.8 V supply. |
URI: | http://dx.doi.org/10.1109/JSSC.2007.905293 http://hdl.handle.net/11536/3930 |
ISSN: | 0018-9200 |
DOI: | 10.1109/JSSC.2007.905293 |
期刊: | IEEE JOURNAL OF SOLID-STATE CIRCUITS |
Volume: | 42 |
Issue: | 10 |
起始頁: | 2149 |
結束頁: | 2160 |
顯示於類別: | 會議論文 |