A CMOS 6-Bit 16-GS/s Time-Interleaved ADC with Digital Background Calibration

標題:	A CMOS 6-Bit 16-GS/s Time-Interleaved ADC with Digital Background Calibration
作者:	Huang, Chun-Cheng Wang, Chung-Yi Wu, Jieh-Tsorng 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics
公開日期:	2010
摘要:	An 8-channel 6-bit 16-GS/s time-interleaved ADC was fabricated using a 65nm CMOS technology. Each A/D channel is a flash ADC using latch-type comparator with background offset calibration. Timing skews among the channels are also continuously calibrated in the background. The chip achieves 42.3dB SFDR and 30.8dB SNDR at 16 GS/s sampling rate.
URI:	http://hdl.handle.net/11536/26965 http://dx.doi.org/10.1109/VLSIC.2010.5560312
ISBN:	978-1-4244-7636-7
DOI:	10.1109/VLSIC.2010.5560312
期刊:	2010 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS
起始頁:	159
結束頁:	160
顯示於類別：	會議論文

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