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dc.contributor.authorFang, Bing-Nanen_US
dc.contributor.authorWu, Jieh-Tsorngen_US
dc.date.accessioned2014-12-08T15:30:05Z-
dc.date.available2014-12-08T15:30:05Z-
dc.date.issued2012en_US
dc.identifier.isbn978-1-4673-0219-7en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/21561-
dc.description.abstractA 10-bit 200-MS/ s pipelined ADC was fabricated using a 90 nm CMOS technology. Switching opamps are used to save power. They are designed for high speed and fast turnon time. Digital background calibration is used to correct the conversion error caused by the low dc gain of the opamps. The ADC consumes 26 mW from a 1.1 V supply. Its measured DNL and INL are + 0.98/-0.81 LSB and + 1.4/-1.5 LSB respectively. Its measured SNDR and SFDR are 55 dB and 67.2 dB respectively. The chip active area is 0.69 mm(2).en_US
dc.language.isoen_USen_US
dc.titleA 10-Bit 200-MS/s Digitally-Calibrated Pipelined ADC Using Switching Opampsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012)en_US
dc.citation.spage1042en_US
dc.citation.epage1045en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000316903701066-
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