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dc.contributor.authorLiu, Wen-Haoen_US
dc.contributor.authorLi, Yih-Langen_US
dc.contributor.authorKoh, Cheng-Koken_US
dc.date.accessioned2014-12-08T15:30:08Z-
dc.date.available2014-12-08T15:30:08Z-
dc.date.issued2012en_US
dc.identifier.isbn978-1-4503-1573-9en_US
dc.identifier.urihttp://hdl.handle.net/11536/21597-
dc.description.abstractConsidering routability issue in the early stages of VLSI design flow can avoid generating an unroutable design. Several recent routablity-driven placers [8-11] adopt a built-in global router to estimate routing congestion. While the routability of the placement solution improves, the performance of these placers degrades. Many of these built-in global router and state-of-the-art academic global routers use maze routing to seek a detoured path. Although very effective, maze routing is relatively slower than other routing algorithms, such as pattern routing and monotonic routing algorithms. This work presents two efficient routing algorithms, called unilateral monotonic routing and hybrid unilateral monotonic routing, to replace maze routing and to realize a highly fast maze-free global router that is suited to act as a built-in routing congestion estimator for placers. Experimental results indicate that RCE achieves similar routing quality when compared with [20], as well as an over 20-fold runtime speedup in large benchmarks.en_US
dc.language.isoen_USen_US
dc.titleA Fast Maze-Free Routing Congestion Estimator With Hybrid Unilateral Monotonic Routingen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2012 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD)en_US
dc.citation.spage713en_US
dc.citation.epage719en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000317001300116-
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