完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Liu, Tung-Yu | en_US |
dc.contributor.author | Lo, Shen-Chuan | en_US |
dc.contributor.author | Sheu, Jeng-Tzong | en_US |
dc.date.accessioned | 2014-12-08T15:30:22Z | - |
dc.date.available | 2014-12-08T15:30:22Z | - |
dc.date.issued | 2013-04-01 | en_US |
dc.identifier.issn | 0741-3106 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/LED.2013.2247737 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/21716 | - |
dc.description.abstract | We investigate the characteristics of single-crystallike (SCL) poly-Si nanowire (SCL poly-Si NW) thin-film-transistors with gate-all-around (GAA) structures. The GAA SCL poly-Si NWs are prepared by a modified sidewall spacer process utilizing an amorphous silicon (alpha-Si) mesa structure. The combination of the high surface-to-volume ratio of the NW and a nominal gate length of 0.25 mu m lead to clear improvement in electrical performance, including a steep subthreshold swing (90 +/- 15 mV/dec), a virtual absence of drain-induced barrier lowering (21 +/- 13 mV/V), and a very high ON/OFF current ratio similar to 7 x 10(7) (V-D = 1 V, V-G = 3 V). | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Gate-all-around (GAA) | en_US |
dc.subject | nanowire (NW) | en_US |
dc.subject | single-crystal-like (SCL) | en_US |
dc.subject | thin film transistor (TFT) | en_US |
dc.title | Gate-All-Around Single-Crystal-Like Poly-Si Nanowire TFTs With a Steep-Subthreshold Slope | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/LED.2013.2247737 | en_US |
dc.identifier.journal | IEEE ELECTRON DEVICE LETTERS | en_US |
dc.citation.volume | 34 | en_US |
dc.citation.issue | 4 | en_US |
dc.citation.spage | 523 | en_US |
dc.citation.epage | 525 | en_US |
dc.contributor.department | 材料科學與工程學系 | zh_TW |
dc.contributor.department | Department of Materials Science and Engineering | en_US |
dc.identifier.wosnumber | WOS:000316813100016 | - |
dc.citation.woscount | 2 | - |
顯示於類別: | 期刊論文 |