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dc.contributor.authorLiu, Tung-Yuen_US
dc.contributor.authorLo, Shen-Chuanen_US
dc.contributor.authorSheu, Jeng-Tzongen_US
dc.date.accessioned2014-12-08T15:30:22Z-
dc.date.available2014-12-08T15:30:22Z-
dc.date.issued2013-04-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2013.2247737en_US
dc.identifier.urihttp://hdl.handle.net/11536/21716-
dc.description.abstractWe investigate the characteristics of single-crystallike (SCL) poly-Si nanowire (SCL poly-Si NW) thin-film-transistors with gate-all-around (GAA) structures. The GAA SCL poly-Si NWs are prepared by a modified sidewall spacer process utilizing an amorphous silicon (alpha-Si) mesa structure. The combination of the high surface-to-volume ratio of the NW and a nominal gate length of 0.25 mu m lead to clear improvement in electrical performance, including a steep subthreshold swing (90 +/- 15 mV/dec), a virtual absence of drain-induced barrier lowering (21 +/- 13 mV/V), and a very high ON/OFF current ratio similar to 7 x 10(7) (V-D = 1 V, V-G = 3 V).en_US
dc.language.isoen_USen_US
dc.subjectGate-all-around (GAA)en_US
dc.subjectnanowire (NW)en_US
dc.subjectsingle-crystal-like (SCL)en_US
dc.subjectthin film transistor (TFT)en_US
dc.titleGate-All-Around Single-Crystal-Like Poly-Si Nanowire TFTs With a Steep-Subthreshold Slopeen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/LED.2013.2247737en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume34en_US
dc.citation.issue4en_US
dc.citation.spage523en_US
dc.citation.epage525en_US
dc.contributor.department材料科學與工程學系zh_TW
dc.contributor.departmentDepartment of Materials Science and Engineeringen_US
dc.identifier.wosnumberWOS:000316813100016-
dc.citation.woscount2-
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