完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lee, Ren-Jie | en_US |
dc.contributor.author | Chen, Hung-Ming | en_US |
dc.date.accessioned | 2014-12-08T15:30:24Z | - |
dc.date.available | 2014-12-08T15:30:24Z | - |
dc.date.issued | 2013-03-01 | en_US |
dc.identifier.issn | 1084-4309 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1145/2442087.2442101 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/21741 | - |
dc.description.abstract | IC-centric design flow has been a common paradigm when designing and optimizing a system. Package and board/system designs are usually followed by almost-ready chip designs, which causes long turn-around time communicating with package and system houses. In this article, the realizations of area-array I/O design methodologies are studied. Different from IC-centric flow, we propose a chip-package concurrent design flow to speed up the design time. Along with the flow, we design the I/O-bump (and P/G-bump) tile that combines I/O (and P/G) and bump into a hard macro with the considerations of I/O power connection and electrostatic discharge (ESD) protection. We then employ an I/O-row based scheme to place I/O-bump tiles with existed metal layers. By such a scheme, it reduces efforts in I/O placement legalization and the redistribution layer (RDL) routing. With the emphasis on package design awareness, the proposed methods map package balls onto chip I/Os, thus providing an opportunity to design chip and package in parallel. Due to this early study of I/O and bump planning, faster convergence can be expected with concurrent design flow. The results are encouraging and the merits of this flow are reassuring. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Algorithms | en_US |
dc.subject | Design | en_US |
dc.subject | Area-array IC design | en_US |
dc.subject | I/O-bump planning | en_US |
dc.subject | chip-package feasibility study | en_US |
dc.subject | concurrent IC design flow | en_US |
dc.title | A Study of Row-Based Area-Array I/O Design Planning in Concurrent Chip-Package Design Flow | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1145/2442087.2442101 | en_US |
dc.identifier.journal | ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS | en_US |
dc.citation.volume | 18 | en_US |
dc.citation.issue | 2 | en_US |
dc.citation.epage | en_US | |
dc.contributor.department | 交大名義發表 | zh_TW |
dc.contributor.department | National Chiao Tung University | en_US |
dc.identifier.wosnumber | WOS:000317427700014 | - |
dc.citation.woscount | 0 | - |
顯示於類別: | 期刊論文 |