Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Tsui, Bing-Yue | en_US |
dc.contributor.author | Su, Ting-Ting | en_US |
dc.contributor.author | Shew, Bor-Yuan | en_US |
dc.contributor.author | Huang, Yang-Tung | en_US |
dc.date.accessioned | 2014-12-08T15:30:24Z | - |
dc.date.available | 2014-12-08T15:30:24Z | - |
dc.date.issued | 2013-03-01 | en_US |
dc.identifier.issn | 0038-1101 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1016/j.sse.2012.11.010 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/21742 | - |
dc.description.abstract | Effect of surface preparation on the radiation hardness of MOS devices with high dielectric constant gate dielectric of HfO2 and metal gate of TiN is studied using extreme ultra-violet (EUV) light as the radiation source. Three kinds of surface treatment including HF-last, chemical-oxidation, and rapid-thermal-oxidation were evaluated. Among them, chemical-oxidation exhibits the best radiation hardiness in terms of interface traps and border traps. The state-of-the-art MOSFET with a thin high-k dielectric and a high quality chemical oxide interfacial layer shows that the degradation of subthreshold swing is more severe than degradation of threshold voltage. However, the overall degradation is less than 6% even after EUV irradiation to a total dose of 580 mJ/cm(2). Off-state current degradation is observed due to the generation of oxide traps and interface traps at the isolation region. This phenomenon does not occur In the conventional optical lithography process but should be considered if EUV lithography is used. (C) 2013 Elsevier Ltd. All rights reserved. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Radiation hardness | en_US |
dc.subject | Extreme ultra-violet (EUV) | en_US |
dc.subject | High dielectric constant dielectric | en_US |
dc.subject | Oxide trap | en_US |
dc.subject | Border trap | en_US |
dc.subject | Interface trap | en_US |
dc.title | Effect of surface preparation on the radiation hardness of high-dielectric constant gate dielectric | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1016/j.sse.2012.11.010 | en_US |
dc.identifier.journal | SOLID-STATE ELECTRONICS | en_US |
dc.citation.volume | 81 | en_US |
dc.citation.issue | en_US | |
dc.citation.spage | 119 | en_US |
dc.citation.epage | 123 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000317444400021 | - |
dc.citation.woscount | 0 | - |
Appears in Collections: | Articles |
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