Design and Analysis of Robust Tunneling FET SRAM

Abstract

With a steep subthreshold slope, tunneling FETs (TFETs) are promising candidates for ultralow-voltage operation compared with conventional MOSFETs. However, the delayed saturation characteristic and the broad soft transition region result in a large crossover region/current in an inverter, thus degrading the hold/read static noise margin (H/RSNM) of TFET SRAM cells. The write-ability and write static noise margin (WSNM) of TFET SRAM cells are constrained by the unidirectional conduction characteristics and large crossover contention of the write access transistor and the holding transistor. In this paper, we present a detailed analysis of TFET circuit switching/output characteristics/performance and the underlying physics. The stability/performance of several TFET SRAM cells are then analyzed/compared using atomistic technology computer-aided design mixed-mode simulations. Finally, a robust 7T driverless (DL) TFET SRAM cell is proposed. The proposed 7T DL TFET SRAM cell, with better output characteristics in single-gate mode, and decoupled read current path from cell storage node and push-pull write action with asymmetrical raised-cell-virtual-ground write-assist, provides a significant improvement in hold, read, and write stability and performance.