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dc.contributor.authorLee, Ko-Huien_US
dc.contributor.authorLin, Horng-Chihen_US
dc.contributor.authorHuang, Tiao-Yuanen_US
dc.date.accessioned2014-12-08T15:30:35Z-
dc.date.available2014-12-08T15:30:35Z-
dc.date.issued2013-06-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2013.2256771en_US
dc.identifier.urihttp://hdl.handle.net/11536/21853-
dc.description.abstractA high-performance short-channel tri-gated polycrystalline-silicon nanowire (NW) field-effect transistor is developed by using simple sidewall spacer and lateral etching techniques without employing costly lithographic tools. Channel length of 120 nm and NW thickness of 25 nm can be easily formed by the self-aligned process. The device exhibits superior electrical characteristics because of the strong gate controllability: a subthreshold swing of 102 mV/dec, drain induced barrier lowing of 74.4 mV/V, and extremely high I-ON/I-OFF ratio of 4.4 x 10(8)(V-d = 1 V) are obtained.en_US
dc.language.isoen_USen_US
dc.subjectNanowireen_US
dc.subjectpolycrystalline-silicon (poly-Si)en_US
dc.subjectself-aligneden_US
dc.subjectshort channelen_US
dc.titleNovel Method for Fabrication of Tri-Gated Poly-Si Nanowire Field-Effect Transistors With Sublithographic Channel Dimensionsen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/LED.2013.2256771en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume34en_US
dc.citation.issue6en_US
dc.citation.spage720en_US
dc.citation.epage722en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000319460800001-
dc.citation.woscount1-
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