Novel Method for Fabrication of Tri-Gated Poly-Si Nanowire Field-Effect Transistors With Sublithographic Channel Dimensions

doi:10.1109/LED.2013.2256771

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Lee, Ko-Hui	en_US
dc.contributor.author	Lin, Horng-Chih	en_US
dc.contributor.author	Huang, Tiao-Yuan	en_US
dc.date.accessioned	2014-12-08T15:30:35Z	-
dc.date.available	2014-12-08T15:30:35Z	-
dc.date.issued	2013-06-01	en_US
dc.identifier.issn	0741-3106	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/LED.2013.2256771	en_US
dc.identifier.uri	http://hdl.handle.net/11536/21853	-
dc.description.abstract	A high-performance short-channel tri-gated polycrystalline-silicon nanowire (NW) field-effect transistor is developed by using simple sidewall spacer and lateral etching techniques without employing costly lithographic tools. Channel length of 120 nm and NW thickness of 25 nm can be easily formed by the self-aligned process. The device exhibits superior electrical characteristics because of the strong gate controllability: a subthreshold swing of 102 mV/dec, drain induced barrier lowing of 74.4 mV/V, and extremely high I-ON/I-OFF ratio of 4.4 x 10(8)(V-d = 1 V) are obtained.	en_US
dc.language.iso	en_US	en_US
dc.subject	Nanowire	en_US
dc.subject	polycrystalline-silicon (poly-Si)	en_US
dc.subject	self-aligned	en_US
dc.subject	short channel	en_US
dc.title	Novel Method for Fabrication of Tri-Gated Poly-Si Nanowire Field-Effect Transistors With Sublithographic Channel Dimensions	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/LED.2013.2256771	en_US
dc.identifier.journal	IEEE ELECTRON DEVICE LETTERS	en_US
dc.citation.volume	34	en_US
dc.citation.issue	6	en_US
dc.citation.spage	720	en_US
dc.citation.epage	722	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000319460800001	-
dc.citation.woscount	1	-
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