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dc.contributor.authorChung, Cheng-Tingen_US
dc.contributor.authorChen, Che-Weien_US
dc.contributor.authorLin, Jyun-Chihen_US
dc.contributor.authorWu, Che-Chenen_US
dc.contributor.authorChien, Chao-Hsinen_US
dc.contributor.authorLuo, Guang-Lien_US
dc.contributor.authorKei, Chi-Chungen_US
dc.contributor.authorHsiao, Chien-Nanen_US
dc.date.accessioned2014-12-08T15:30:35Z-
dc.date.available2014-12-08T15:30:35Z-
dc.date.issued2013-06-01en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TED.2013.2259173en_US
dc.identifier.urihttp://hdl.handle.net/11536/21857-
dc.description.abstractIntegrating germanium (Ge) thin film on silicon-on-insulator (SOI) substrate and fabricating Ge fin field-effect transistors (FinFETs) are demonstrated in this paper. Directly grown Ge film on a high-resistivity thin SOI substrate provides a good platform for fabricating advanced Ge devices. The SOI structure could effectively suppress junction leakage; therefore, high I-ON/I-OFF ratio (similar to 5 x 10(5), at V-D = 0.1 V) of the drain current is achieved. Tri-gate structure provides better short-channel control abilities for the Ge FinFETs, and the drain-induced barrier lowering and threshold voltage (V-TH) shift can be maintained at the level of similar to 110 mV/V and similar to 0.1 V, respectively, for Ge n-channel FinFET with L-channel = 120 nm and W-Fin = 40 nm. Multifin Ge FinFET with L-channel = 170 nm and W-Fin = 50 nm is also illustrated. Both N-and P-FinFETs possess high I-ON/I-OFF ratio over 104. Besides, the subthreshold swing could be reduced around 25% after forming gas annealing.en_US
dc.language.isoen_USen_US
dc.subjectEpitaxial Ge on silicon on-insulator (SOI) substratesen_US
dc.subjectfin field-effect transistors (FinFETs)en_US
dc.subjectforming gas annealingen_US
dc.subjectGe CMOSen_US
dc.subjectgermaniumen_US
dc.titleEpitaxial Germanium on SOI Substrate and Its Application of Fabricating High I-ON/I-OFF Ratio Ge FinFETsen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TED.2013.2259173en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume60en_US
dc.citation.issue6en_US
dc.citation.spage1878en_US
dc.citation.epage1883en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000319355500012-
dc.citation.woscount4-
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