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dc.contributor.authorYeh, Mu-Shihen_US
dc.contributor.authorWu, Yung-Chunen_US
dc.contributor.authorHung, Min-Fengen_US
dc.contributor.authorLiu, Kuan-Chengen_US
dc.contributor.authorJhan, Yi-Rueien_US
dc.contributor.authorChen, Lun-Chunen_US
dc.contributor.authorChang, Chun-Yenen_US
dc.date.accessioned2014-12-08T15:31:09Z-
dc.date.available2014-12-08T15:31:09Z-
dc.date.issued2013-07-22en_US
dc.identifier.issn1931-7573en_US
dc.identifier.urihttp://dx.doi.org/10.1186/1556-276X-8-331en_US
dc.identifier.urihttp://hdl.handle.net/11536/22184-
dc.description.abstractThis study proposed the twin poly-Si fin field-effect transistor (FinFET) nonvolatile memory with a structure that is composed of Omega-gate nanowires (NWs). Experimental results show that the NW device has superior memory characteristics because its Omega-gate structure provides a large memory window and high program/erase efficiency. With respect to endurance and retention, the memory window can be maintained at 3.5 V after 10(4) program and erase cycles, and after 10 years, the charge is 47.7% of its initial value. This investigation explores its feasibility in the future active matrix liquid crystal display system-on-panel and three-dimensional stacked flash memory applications.en_US
dc.language.isoen_USen_US
dc.subjectTwin poly-Sien_US
dc.subjectFinFETen_US
dc.subjectTFTen_US
dc.subjectNonvolatile memoryen_US
dc.subjectOmega-gateen_US
dc.subjectNanowiresen_US
dc.subjectThree-dimensionalen_US
dc.subjectFlash memoryen_US
dc.titleFabrication, characterization and simulation of Omega-gate twin poly-Si FinFET nonvolatile memoryen_US
dc.typeArticleen_US
dc.identifier.doi10.1186/1556-276X-8-331en_US
dc.identifier.journalNANOSCALE RESEARCH LETTERSen_US
dc.citation.volume8en_US
dc.citation.issueen_US
dc.citation.epageen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000322786200001-
dc.citation.woscount1-
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