Precoder/two-stage equaliser for block-based single-carrier transmission with insufficient guard interval

doi:10.1049/el.2011.0559

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Song, Y.	en_US
dc.contributor.author	Fung, C. C.	en_US
dc.contributor.author	Wong, K. T.	en_US
dc.contributor.author	Meng, H.	en_US
dc.contributor.author	Tseng, D. -F.	en_US
dc.date.accessioned	2014-12-08T15:31:51Z	-
dc.date.available	2014-12-08T15:31:51Z	-
dc.date.issued	2011-06-23	en_US
dc.identifier.issn	0013-5194	en_US
dc.identifier.uri	http://dx.doi.org/10.1049/el.2011.0559	en_US
dc.identifier.uri	http://hdl.handle.net/11536/22497	-
dc.description.abstract	Proposed is a zero-inserting precoder and a two-stage linear equaliser, to shorten the guard interval in block-based single-carrier modulation. The first-stage equaliser consists of a linear single-tapper-subcarrier frequency-domain equaliser. The second-stage equaliser maximises the SINR, in the time-domain, based on the interference-plus-noise estimated from the zero-padded sub-intervals of the single-carrier modulation. This proposed scheme is applicable even without cyclic prefixing.	en_US
dc.language.iso	en_US	en_US
dc.title	Precoder/two-stage equaliser for block-based single-carrier transmission with insufficient guard interval	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1049/el.2011.0559	en_US
dc.identifier.journal	ELECTRONICS LETTERS	en_US
dc.citation.volume	47	en_US
dc.citation.issue	13	en_US
dc.citation.spage	746	en_US
dc.citation.epage	747	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000291928100012	-
dc.citation.woscount	1	-
顯示於類別：	期刊論文

文件中的檔案：

000291928100012.pdf

若為 zip 檔案，請下載檔案解壓縮後，用瀏覽器開啟資料夾中的 index.html 瀏覽全文。