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dc.contributor.authorLin, Yi-Minen_US
dc.contributor.authorChang, Hsie-Chiaen_US
dc.contributor.authorLee, Chen-Yien_US
dc.date.accessioned2014-12-08T15:32:14Z-
dc.date.available2014-12-08T15:32:14Z-
dc.date.issued2013-11-01en_US
dc.identifier.issn1063-8210en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TVLSI.2012.2227847en_US
dc.identifier.urihttp://hdl.handle.net/11536/22675-
dc.description.abstractCompared with traditonal hard Bose-Chaudhuri-Hochquenghem (BCH) decoders, soft BCH decoders provide better error-correcting performance but much higher hardware complexity. In this brief, an improved soft BCH decoding algorithm is presented to achieve both competitive hardware complexity and better error-correcting performance by dealing with least reliable bits and compensating one extra error outside the least reliable set. For BCH (255, 239; 2) and (255, 231; 3) codes, our proposed soft BCH decoders can achieve up to 0.75-dB coding gain with one extra error compensation and 5% less complexity than the traditional hard BCH decoders.en_US
dc.language.isoen_USen_US
dc.subjectBose-Chaudhuri-Hochquenghem (BCH) codesen_US
dc.subjecterror-correction codingen_US
dc.subjectsoft decodingen_US
dc.titleImproved High Code-Rate Soft BCH Decoder Architectures With One Extra Error Compensationen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TVLSI.2012.2227847en_US
dc.identifier.journalIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMSen_US
dc.citation.volume21en_US
dc.citation.issue11en_US
dc.citation.spage2160en_US
dc.citation.epage2164en_US
dc.contributor.department電機工程學系zh_TW
dc.contributor.departmentDepartment of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000325227200018-
dc.citation.woscount0-
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