完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lin, Yi-Min | en_US |
dc.contributor.author | Chang, Hsie-Chia | en_US |
dc.contributor.author | Lee, Chen-Yi | en_US |
dc.date.accessioned | 2014-12-08T15:32:14Z | - |
dc.date.available | 2014-12-08T15:32:14Z | - |
dc.date.issued | 2013-11-01 | en_US |
dc.identifier.issn | 1063-8210 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TVLSI.2012.2227847 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/22675 | - |
dc.description.abstract | Compared with traditonal hard Bose-Chaudhuri-Hochquenghem (BCH) decoders, soft BCH decoders provide better error-correcting performance but much higher hardware complexity. In this brief, an improved soft BCH decoding algorithm is presented to achieve both competitive hardware complexity and better error-correcting performance by dealing with least reliable bits and compensating one extra error outside the least reliable set. For BCH (255, 239; 2) and (255, 231; 3) codes, our proposed soft BCH decoders can achieve up to 0.75-dB coding gain with one extra error compensation and 5% less complexity than the traditional hard BCH decoders. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Bose-Chaudhuri-Hochquenghem (BCH) codes | en_US |
dc.subject | error-correction coding | en_US |
dc.subject | soft decoding | en_US |
dc.title | Improved High Code-Rate Soft BCH Decoder Architectures With One Extra Error Compensation | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TVLSI.2012.2227847 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | en_US |
dc.citation.volume | 21 | en_US |
dc.citation.issue | 11 | en_US |
dc.citation.spage | 2160 | en_US |
dc.citation.epage | 2164 | en_US |
dc.contributor.department | 電機工程學系 | zh_TW |
dc.contributor.department | Department of Electrical and Computer Engineering | en_US |
dc.identifier.wosnumber | WOS:000325227200018 | - |
dc.citation.woscount | 0 | - |
顯示於類別: | 期刊論文 |