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dc.contributor.authorKer, Ming-Douen_US
dc.contributor.authorChiu, Po-Yenen_US
dc.date.accessioned2014-12-08T15:32:16Z-
dc.date.available2014-12-08T15:32:16Z-
dc.date.issued2013-10-01en_US
dc.identifier.issn1549-8328en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCSI.2013.2244351en_US
dc.identifier.urihttp://hdl.handle.net/11536/22696-
dc.description.abstractA new 2 x V-DD-tolerant input/output (I/O) buffer with process, voltage, and temperature (PVT) compensation is proposed and verified in a 90-nm CMOS process. Consisting of the dynamic source bias and gate controlled technique, the proposed mixed-voltage I/O buffer realized by only 1xV(DD) devices can successfully transmit and receive 2 x V-DD signal. Utilizing this technique with only 1xV(DD) devices, the digital logic gates are also modified to have 2xV(DD)-tolerant capability. With 2xV(DD)-tolerant logic gates, the PVT variation detector has been implemented to detect PVT variations from 2 x V-DD signal and provide compensation control to the 2 x V-DD-tolerant I/O buffer without suffering the gate-oxide overstress issue.en_US
dc.language.isoen_USen_US
dc.subjectGate-oxide overstressen_US
dc.subjectmixed-voltage I/O bufferen_US
dc.subjectprocess, voltage, and temperature (PVT) variationen_US
dc.titleDesign of 2 x V-DD-Tolerant I/O Buffer With PVT Compensation Realized by Only 1 x V-DD Thin-Oxide Devicesen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCSI.2013.2244351en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERSen_US
dc.citation.volume60en_US
dc.citation.issue10en_US
dc.citation.spage2549en_US
dc.citation.epage2560en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.department生醫電子轉譯研究中心zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.contributor.departmentBiomedical Electronics Translational Research Centeren_US
dc.identifier.wosnumberWOS:000325225700001-
dc.citation.woscount0-
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