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dc.contributor.authorHsieh, E. R.en_US
dc.contributor.authorWu, P. C.en_US
dc.contributor.authorChung, Steve S.en_US
dc.contributor.authorTsai, C. H.en_US
dc.contributor.authorHuang, R. M.en_US
dc.contributor.authorTsai, C. T.en_US
dc.date.accessioned2014-12-08T15:32:43Z-
dc.date.available2014-12-08T15:32:43Z-
dc.date.issued2013en_US
dc.identifier.isbn978-1-4673-3082-4en_US
dc.identifier.issn1524-766Xen_US
dc.identifier.urihttp://hdl.handle.net/11536/22854-
dc.description.abstractThe manipulation of RTN-trap profiling bas been experimentally demonstrated on both planar and trigate MOSFETs. It was achieved by a simple experimental method to take the 2D profiling of the RTN-trap in both oxide depth (vertical) and channel (lateral) directions in the gate oxide. Then, by arranging various 2D fields for the device stress condition, the positions of RTN traps can be precisely controlled. This is the first being reported that the positions of RTN-traps can be manipulated, showing significant advances for the understanding of the trap generation and the impact on the device reliability. Results have demonstrated why trigate exhibits much worse reliability than the planar ones.en_US
dc.language.isoen_USen_US
dc.titleThe Understanding of the Bulk Trigate MOSFET's Reliability Through the Manipulation of RTN Trapsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2013 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS (VLSI-TSA)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000326324800023-
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