標題: | Electrical Performances and Structural Designs of Copper Bonding in Wafer-Level Three-Dimensional Integration |
作者: | Chen, K. N. Young, A. M. Lee, S. H. Lu, J. -Q. 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Three-Dimensional Integration;3D IC;Wafer Bonding;Cu Bonding |
公開日期: | 1-六月-2011 |
摘要: | The integrity of bonded Cu interconnects in wafer-level three-dimensional integration has been investigated as the function of pattern size and density, as well as bonding process parameter. The desired pattern density coupled with the application of bonding process profile we developed gives optimal yield and alignment accuracy, and provides excellent electrical connectivity and contact resistance through the entire wafer. This result is a key milestone in establishing the manufacturability of Cu-based interconnections for 3D integration technology. |
URI: | http://dx.doi.org/10.1166/jnn.2011.4149 http://hdl.handle.net/11536/23069 |
ISSN: | 1533-4880 |
DOI: | 10.1166/jnn.2011.4149 |
期刊: | JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY |
Volume: | 11 |
Issue: | 6 |
起始頁: | 5143 |
結束頁: | 5147 |
顯示於類別: | 期刊論文 |