完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lin, Cosette Y. H. | en_US |
dc.contributor.author | Huang, Ryan H. -M. | en_US |
dc.contributor.author | Wen, Charles H. -P. | en_US |
dc.contributor.author | Chang, Austin C. -C. | en_US |
dc.date.accessioned | 2014-12-08T15:33:13Z | - |
dc.date.available | 2014-12-08T15:33:13Z | - |
dc.date.issued | 2013 | en_US |
dc.identifier.isbn | 978-1-4673-4436-4 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/23094 | - |
dc.description.abstract | Aging and soft errors have become the two most critical reliability issues for nano-scaled CMOS designs. In this paper, the aging effect due to negative bias temperature instability (NBTI) is first analyzed on cells using a 45nm CMOS technology for soft errors. Second, an accurate statistical soft-error-rate (SSER) framework is built and incorporates the aging-aware cell models. As a result, two findings are discovered: (1) PMOS-induced transient faults, comparing to NMOS-induced ones, have more variation in pulse widths since PMOS is more susceptible to NBTI; (2) NBTI together with process variation, induces more soft errors (similar to 19%) and thus needs to be considered, simultaneously, during circuit analysis. Experimental result shows that our SSER framework considering both process variation and aging is efficient (with multiple-order speedups) and achieves high accuracy (with <3% errors) when compared with Monte-Carlo SPICE simulation. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Aging-aware Statistical Soft-Error-Rate Analysis for Nano-Scaled CMOS Designs | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT) | en_US |
dc.contributor.department | 電機資訊學士班 | zh_TW |
dc.contributor.department | Undergraduate Honors Program of Electrical Engineering and Computer Science | en_US |
dc.identifier.wosnumber | WOS:000326882100051 | - |
顯示於類別: | 會議論文 |