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dc.contributor.authorChang, Hsiu-Chien_US
dc.contributor.authorChen, Chih-Lungen_US
dc.contributor.authorChang, Hsie-Chiaen_US
dc.date.accessioned2014-12-08T15:33:44Z-
dc.date.available2014-12-08T15:33:44Z-
dc.date.issued2013-10-01en_US
dc.identifier.issn1089-7798en_US
dc.identifier.urihttp://dx.doi.org/10.1109/LCOMM.2013.082413.131191en_US
dc.identifier.urihttp://hdl.handle.net/11536/23315-
dc.description.abstractAn iterative weighted reliability two-step majority logic decoding (IWRTS-MLGD) algorithm for two-step majority-logic (TS-MLG)-decodable cyclic codes is presented. In contrast to other message passing decoding algorithms that utilize real number operations, our proposed decoding algorithm requires only logical operations and integer additions. Therefore, large computational complexities can be reduced. For moderate-length TS-MLG-decodable cyclic codes, the proposed algorithm aided with soft information and a scaling factor outperforms the hard-decision TS-MLGD algorithm and hard-decision BCH codes with similar length by 1.2- and 1.0-dB, respectively.en_US
dc.language.isoen_USen_US
dc.subjectFinite geometry codeen_US
dc.subjectreliability-based message passing algorithmen_US
dc.subjecttwo-fold EG codeen_US
dc.subjectcyclic codeen_US
dc.titleAn Iterative Weighted Reliability Decoding Algorithm for Two-Step Majority-Logic Decodable Cyclic Codesen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/LCOMM.2013.082413.131191en_US
dc.identifier.journalIEEE COMMUNICATIONS LETTERSen_US
dc.citation.volume17en_US
dc.citation.issue10en_US
dc.citation.spage1980en_US
dc.citation.epage1983en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000326734400028-
dc.citation.woscount1-
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