完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Wang, Jyh-Liang | en_US |
dc.contributor.author | Yang, Po-Yu | en_US |
dc.contributor.author | Juang, Miin-Horng | en_US |
dc.contributor.author | Hsieh, Tsang-Yen | en_US |
dc.contributor.author | Hwang, Chuan-Chou | en_US |
dc.contributor.author | Juan, Chuan-Ping | en_US |
dc.contributor.author | Lee, I-Che | en_US |
dc.date.accessioned | 2014-12-08T15:33:46Z | - |
dc.date.available | 2014-12-08T15:33:46Z | - |
dc.date.issued | 2013-09-01 | en_US |
dc.identifier.issn | 0257-8972 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1016/j.surfcoat.2012.02.029 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/23331 | - |
dc.description.abstract | Transparent high-performance ZnO TFTs have been fabricated via low-temperature hydrothermal method. The dip of H3PO4 solution prior to the hydrothermal process can form the under-cut AZO seed layer and benefit for the control of ZnO growth. While the use of under-cut AZO seed layer with proper design of channel length, the lateral ZnO growth can be artificially controlled in the desired location to make a continuous active-layer and nearly single one vertical grain boundary cross to the current flow in the channel region. ZnO TFTs indicate the behavior of n-channel enhancement-mode devices. The optimum design of channel length (i.e. L=10 mu m) can provide enough space for the lateral growth of large ZnO grains with less channel defects and bring about the advanced device characteristics (i.e. the positive threshold voltage of 3.0 V, mobility of 9.03 cm(2)/V.s, on/off current ratio >10(6), gate leakage of <1 nA with less fluctuation, and extremely high drain current >500 mu A). (C) 2012 Elsevier B.V. All rights reserved. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Zinc oxide (ZnO) | en_US |
dc.subject | Hydrothermal growth (HTG) | en_US |
dc.subject | Thin-film transistors (TFTs) | en_US |
dc.subject | Active-layer | en_US |
dc.subject | Lateral growth | en_US |
dc.title | Zinc oxide thin-film transistors fabricated via low-temperature hydrothermal method | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1016/j.surfcoat.2012.02.029 | en_US |
dc.identifier.journal | SURFACE & COATINGS TECHNOLOGY | en_US |
dc.citation.volume | 231 | en_US |
dc.citation.issue | en_US | |
dc.citation.spage | 428 | en_US |
dc.citation.epage | 432 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000328094200090 | - |
dc.citation.woscount | 0 | - |
顯示於類別: | 期刊論文 |