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dc.contributor.authorCHENG, HCen_US
dc.contributor.authorJUANG, MHen_US
dc.contributor.authorLIN, CTen_US
dc.contributor.authorHUANG, LMen_US
dc.date.accessioned2014-12-08T15:03:48Z-
dc.date.available2014-12-08T15:03:48Z-
dc.date.issued1994-09-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://dx.doi.org/10.1109/55.311128en_US
dc.identifier.urihttp://hdl.handle.net/11536/2340-
dc.description.abstractA process consideration for forming silicided shallow junctions, arising from silicidation process, has been discussed. The CoSi2 shallow p+n junctions formed by various schemes are characterized. The scheme that implants BF2+ ions into thin Co films on Si substrates and subsequent silicidation yields good junctions, but the problems about the dopant drive-in and knock-on of metal deeply degrade this scheme. In the regime that implants the dopant into Si and then Co deposition, however, a large perimeter leakage of 0.1 nA/cm is caused. Generation current, associated with a defect-enhanced diffusion of Co in Si during silicidation, dominates the leakage. A high-temperature pre-activation prior to Co deposition reduces the perimeter leakage to 0.038 nA/cm, but which deepens the junctions.en_US
dc.language.isoen_USen_US
dc.titleA SILICIDATION-INDUCED PROCESS CONSIDERATION FOR FORMING SCALE-DOWN SILICIDED JUNCTIONen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/55.311128en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume15en_US
dc.citation.issue9en_US
dc.citation.spage342en_US
dc.citation.epage344en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:A1994PE79800008-
dc.citation.woscount19-
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