完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | CHENG, HC | en_US |
dc.contributor.author | JUANG, MH | en_US |
dc.contributor.author | LIN, CT | en_US |
dc.contributor.author | HUANG, LM | en_US |
dc.date.accessioned | 2014-12-08T15:03:48Z | - |
dc.date.available | 2014-12-08T15:03:48Z | - |
dc.date.issued | 1994-09-01 | en_US |
dc.identifier.issn | 0741-3106 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/55.311128 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/2340 | - |
dc.description.abstract | A process consideration for forming silicided shallow junctions, arising from silicidation process, has been discussed. The CoSi2 shallow p+n junctions formed by various schemes are characterized. The scheme that implants BF2+ ions into thin Co films on Si substrates and subsequent silicidation yields good junctions, but the problems about the dopant drive-in and knock-on of metal deeply degrade this scheme. In the regime that implants the dopant into Si and then Co deposition, however, a large perimeter leakage of 0.1 nA/cm is caused. Generation current, associated with a defect-enhanced diffusion of Co in Si during silicidation, dominates the leakage. A high-temperature pre-activation prior to Co deposition reduces the perimeter leakage to 0.038 nA/cm, but which deepens the junctions. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A SILICIDATION-INDUCED PROCESS CONSIDERATION FOR FORMING SCALE-DOWN SILICIDED JUNCTION | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/55.311128 | en_US |
dc.identifier.journal | IEEE ELECTRON DEVICE LETTERS | en_US |
dc.citation.volume | 15 | en_US |
dc.citation.issue | 9 | en_US |
dc.citation.spage | 342 | en_US |
dc.citation.epage | 344 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:A1994PE79800008 | - |
dc.citation.woscount | 19 | - |
顯示於類別: | 期刊論文 |