標題: | A 446.6K-Gates 0.55-1.2V H.265/HEVC Decoder for Next Generation Video Applications |
作者: | Tsai, Chang-Hung Wang, Hsiuan-Ting Liu, Chia-Lin Li, Yao Lee, Chen-Yi 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2013 |
摘要: | An architecture of H. 265/HEVC video decoder for next generation video applications is presented. By exploiting near-lossless data compression and Sharing Above Line Buffer (SALB) schemes, both memory bandwidth and on-chip storage can be reduced. Moreover, cross-stage scheduling is applied to the 4-stage decoding pipeline to minimize idle computations. Fabricated in 90nm 1P9M CMOS process, the test chip of the proposed H. 265/HEVC video decoder occupies an area of 1.60x1.98mm(2) to achieve 1080p@30fps and 720p@30fps real-time decoding with power consumption of 36.90 and 9.57mW. |
URI: | http://hdl.handle.net/11536/23725 |
ISBN: | 978-1-4799-0277-4978-1-4799-0280-4 |
期刊: | PROCEEDINGS OF THE 2013 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC) |
起始頁: | 305 |
結束頁: | 308 |
Appears in Collections: | Conferences Paper |