完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Tien, Po-Lung | en_US |
dc.contributor.author | Ke, Bo-Yu | en_US |
dc.date.accessioned | 2014-12-08T15:35:16Z | - |
dc.date.available | 2014-12-08T15:35:16Z | - |
dc.date.issued | 2013 | en_US |
dc.identifier.isbn | 978-1-4673-4620-7 | en_US |
dc.identifier.issn | 2325-5595 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/23905 | - |
dc.description.abstract | Packet scheduling for WDM optical switching systems requires exceedingly low latency processing, making it impractical to be realized by non-parallel based algorithms. In this paper, we propose a new recurrent discrete-time synchronous ranked neural-network (DSRN) for parallel prioritized scheduling. The DSRN is structured with ranked neurons and is capable of operating in a fully parallel (i.e., synchronous) discrete-time manner, and thus can be implemented in digital systems. We then design a DSRN scheduler for a previously proposed experimental WDM optical switching system (WOPIS). For newly arriving packets, the DSRN scheduler determines in real time an optimal set of input/output paths within WOPIS, achieving maximal throughput and priority differentiation subject to the switch-and buffer-contention-free constraints. We delineate via a theorem that DSRN will converge to the optimal solution. The theorem also provides a theoretical upper bound of the convergence latency, O(H), where H is the switch port count. Finally, we demonstrate that, via CUDA-based simulations, the DSRN scheduler achieves near-optimal throughput and prioritized scheduling, with nearly O(logH) convergence latency. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | optical interconnect | en_US |
dc.subject | optical switch | en_US |
dc.subject | parallel scheduling | en_US |
dc.subject | neural networks | en_US |
dc.subject | Quality of Service (QoS) | en_US |
dc.title | Parallel Prioritized Scheduling for WDM Optical Switching System | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2013 IEEE 14TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE SWITCHING AND ROUTING (HPSR) | en_US |
dc.citation.spage | 86 | en_US |
dc.citation.epage | 91 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000333337700014 | - |
顯示於類別: | 會議論文 |