A Switchable Digital-Analog Low-Dropout Regulator for Analog Dynamic Voltage Scaling Technique

Abstract

Dual dynamic voltage scaling (DVS) techniques employed in single-inductor dual-output (SIDO) converters are used to improve the efficiency of the system-on-a-chip (SoC). One DVS technique for digital circuits is controlled by the SoC processor. This paper presents the analog DVS (ADVS) technique for analog circuits to scale voltage across the power MOSFET of the switchable digital-analog (D/A) low-dropout (LDO) regulator which is the post-regulator cascaded in series with the SIDO converter. The ADVS determines the tradeoff between voltage suppression and efficiency. Furthermore, because of the digital operation of the D/A LDO regulator, the quiescent current is further reduced at light loads while the load current requirement is minimized. In addition, the limitation of the capacitor-free LDO is significantly reduced by a few microamperes. The test chip was fabricated using a 40-nm CMOS process. Experimental results demonstrated switchable D/A LDO regulator operation with peak efficiency at 96.7% in analog operation and a 5-mV output voltage ripple at 120-mA load resulting from the advantage of ripple suppression. The power efficiency could be sustained at a value over 92.57% even when the load current decreased to 1 mu A.