Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lin, Mu-Shan | en_US |
dc.contributor.author | Tsai, Chien-Chun | en_US |
dc.contributor.author | Chang, Chih-Hsien | en_US |
dc.contributor.author | Huang, Wen-Hung | en_US |
dc.contributor.author | Hsu, Ying-Yu | en_US |
dc.contributor.author | Yang, Shu-Chun | en_US |
dc.contributor.author | Fu, Chin-Ming | en_US |
dc.contributor.author | Chou, Mao-Hsuan | en_US |
dc.contributor.author | Huang, Tien-Chien | en_US |
dc.contributor.author | Chen, Ching-Fang | en_US |
dc.contributor.author | Huang, Tze-Chiang | en_US |
dc.contributor.author | Adham, Saman | en_US |
dc.contributor.author | Wang, Min-Jer | en_US |
dc.contributor.author | Shen, William Wu | en_US |
dc.contributor.author | Mehta, Ashok | en_US |
dc.date.accessioned | 2014-12-08T15:35:53Z | - |
dc.date.available | 2014-12-08T15:35:53Z | - |
dc.date.issued | 2014-04-01 | en_US |
dc.identifier.issn | 0018-9200 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/JSSC.2013.2297399 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/24264 | - |
dc.description.abstract | A 1 Tbit/ s bandwidth PHY is demonstrated through CoWoS(TM) platform. Two chips: SOC and embedded DRAM ( eDRAM), have been fabricated in TSMC 40 nm CMOS technology and stacked on a silicon interposer chip. 1024 DQ buses operating at 1.1 Gbit/ s with VDDQ = 0.3 V are proven between SOC chip and eDRAM chip in experimental results with 1 mm signal trace length on the silicon interposer. A novel timing compensation mechanism is presented to achieve a low- power and small area eDRAM PHY that excludes PLL/ DLL but retains good timing margin. Another data sampling alignment training approach is employed to enhance timing robustness. A compact low- swing IO also achieves power efficiency of 0.105 mW/ Gbps. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Chip on wafer on substrate | en_US |
dc.subject | CoWoS | en_US |
dc.subject | DLL | en_US |
dc.subject | eDRAM | en_US |
dc.subject | low-swing IO | en_US |
dc.subject | micro-bump | en_US |
dc.subject | PHY | en_US |
dc.subject | PLL | en_US |
dc.subject | SII | en_US |
dc.subject | silicon-interposer | en_US |
dc.subject | timing compensation | en_US |
dc.subject | 2.5D-IC. | en_US |
dc.title | A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/JSSC.2013.2297399 | en_US |
dc.identifier.journal | IEEE JOURNAL OF SOLID-STATE CIRCUITS | en_US |
dc.citation.volume | 49 | en_US |
dc.citation.issue | 4 | en_US |
dc.citation.spage | 1063 | en_US |
dc.citation.epage | 1074 | en_US |
dc.contributor.department | 交大名義發表 | zh_TW |
dc.contributor.department | National Chiao Tung University | en_US |
dc.identifier.wosnumber | WOS:000334114600024 | - |
dc.citation.woscount | 1 | - |
Appears in Collections: | Articles |
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