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dc.contributor.authorLin, Mu-Shanen_US
dc.contributor.authorTsai, Chien-Chunen_US
dc.contributor.authorChang, Chih-Hsienen_US
dc.contributor.authorHuang, Wen-Hungen_US
dc.contributor.authorHsu, Ying-Yuen_US
dc.contributor.authorYang, Shu-Chunen_US
dc.contributor.authorFu, Chin-Mingen_US
dc.contributor.authorChou, Mao-Hsuanen_US
dc.contributor.authorHuang, Tien-Chienen_US
dc.contributor.authorChen, Ching-Fangen_US
dc.contributor.authorHuang, Tze-Chiangen_US
dc.contributor.authorAdham, Samanen_US
dc.contributor.authorWang, Min-Jeren_US
dc.contributor.authorShen, William Wuen_US
dc.contributor.authorMehta, Ashoken_US
dc.date.accessioned2014-12-08T15:35:53Z-
dc.date.available2014-12-08T15:35:53Z-
dc.date.issued2014-04-01en_US
dc.identifier.issn0018-9200en_US
dc.identifier.urihttp://dx.doi.org/10.1109/JSSC.2013.2297399en_US
dc.identifier.urihttp://hdl.handle.net/11536/24264-
dc.description.abstractA 1 Tbit/ s bandwidth PHY is demonstrated through CoWoS(TM) platform. Two chips: SOC and embedded DRAM ( eDRAM), have been fabricated in TSMC 40 nm CMOS technology and stacked on a silicon interposer chip. 1024 DQ buses operating at 1.1 Gbit/ s with VDDQ = 0.3 V are proven between SOC chip and eDRAM chip in experimental results with 1 mm signal trace length on the silicon interposer. A novel timing compensation mechanism is presented to achieve a low- power and small area eDRAM PHY that excludes PLL/ DLL but retains good timing margin. Another data sampling alignment training approach is employed to enhance timing robustness. A compact low- swing IO also achieves power efficiency of 0.105 mW/ Gbps.en_US
dc.language.isoen_USen_US
dc.subjectChip on wafer on substrateen_US
dc.subjectCoWoSen_US
dc.subjectDLLen_US
dc.subjecteDRAMen_US
dc.subjectlow-swing IOen_US
dc.subjectmicro-bumpen_US
dc.subjectPHYen_US
dc.subjectPLLen_US
dc.subjectSIIen_US
dc.subjectsilicon-interposeren_US
dc.subjecttiming compensationen_US
dc.subject2.5D-IC.en_US
dc.titleA 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Applicationen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/JSSC.2013.2297399en_US
dc.identifier.journalIEEE JOURNAL OF SOLID-STATE CIRCUITSen_US
dc.citation.volume49en_US
dc.citation.issue4en_US
dc.citation.spage1063en_US
dc.citation.epage1074en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000334114600024-
dc.citation.woscount1-
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