Interface morphology and electrical properties of bonded GaAs/GaAs wafers at different temperatures

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Chang, S. C.	en_US
dc.contributor.author	Wu, Y. S.	en_US
dc.contributor.author	Chang, N.	en_US
dc.date.accessioned	2014-12-08T15:36:14Z	-
dc.date.available	2014-12-08T15:36:14Z	-
dc.date.issued	2012	en_US
dc.identifier.isbn	978-1-60768-355-1	en_US
dc.identifier.issn	1938-5862	en_US
dc.identifier.uri	http://hdl.handle.net/11536/24564	-
dc.identifier.uri	http://dx.doi.org/10.1149/05007.0109ecst	en_US
dc.description.abstract	The microstructure and electrical properties of p-GaAs/n-GaAs bonded interface were investigated. It was observed that when bonding temperature increased from 600 to 800 degrees C, the thickness of oxide layer decreased. Current-voltage characteristic shows typical diode behaviors in these temperature ranges.	en_US
dc.language.iso	en_US	en_US
dc.title	Interface morphology and electrical properties of bonded GaAs/GaAs wafers at different temperatures	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.doi	10.1149/05007.0109ecst	en_US
dc.identifier.journal	SEMICONDUCTOR WAFER BONDING 12: SCIENCE, TECHNOLOGY, AND APPLICATIONS	en_US
dc.citation.volume	50	en_US
dc.citation.issue	7	en_US
dc.citation.spage	109	en_US
dc.citation.epage	112	en_US
dc.contributor.department	材料科學與工程學系	zh_TW
dc.contributor.department	Department of Materials Science and Engineering	en_US
dc.identifier.wosnumber	WOS:000337787200013	-
顯示於類別：	會議論文