完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | YEH, CF | en_US |
dc.contributor.author | CHEN, CL | en_US |
dc.date.accessioned | 2014-12-08T15:03:56Z | - |
dc.date.available | 2014-12-08T15:03:56Z | - |
dc.date.issued | 1994-06-01 | en_US |
dc.identifier.issn | 0268-1242 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1088/0268-1242/9/6/015 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/2459 | - |
dc.description.abstract | In multilevel interconnection processes, because thermal stress affects device characteristics and wiring reliability, low-temperature deposition has been required for interlayer dielectrics (SiO2). This research investigated high growth rate and selective growth conditions of room-temperature interlayer dielectrics formed using the liquid-phase deposition method. The dependence of deposition rate on growth temperature and H3BO3 concentration is confirmed, and a concentration of 3.8 mol l-1 of H2SiF6 is used to achieve a high deposition rate of 1250 angstrom h-1. The degree of supersaturation of silica of the immersing solution is found to define three ranges of growth conditions: the non-deposition range, selective deposition range, and conformal deposition range. A selective deposition model is proposed to clarify the mechanism of room-temperature selective SiO2 growth, | en_US |
dc.language.iso | en_US | en_US |
dc.title | ROOM-TEMPERATURE SELECTIVE GROWTH OF DIELECTRIC FILMS BY LIQUID-PHASE DEPOSITION | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1088/0268-1242/9/6/015 | en_US |
dc.identifier.journal | SEMICONDUCTOR SCIENCE AND TECHNOLOGY | en_US |
dc.citation.volume | 9 | en_US |
dc.citation.issue | 6 | en_US |
dc.citation.spage | 1250 | en_US |
dc.citation.epage | 1254 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:A1994NQ79100015 | - |
dc.citation.woscount | 14 | - |
顯示於類別: | 期刊論文 |