Local CDM ESD Protection Circuits for Cross-Power Domains in 3D IC Applications

doi:10.1109/TDMR.2014.2320538

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Chen, Shih-Hung	en_US
dc.contributor.author	Linten, Dimitri	en_US
dc.contributor.author	Scholz, Mirko	en_US
dc.contributor.author	Huang, Yu-Ching	en_US
dc.contributor.author	Hellings, Geert	en_US
dc.contributor.author	Boschke, Roman	en_US
dc.contributor.author	Ker, Ming-Dou	en_US
dc.contributor.author	Groeseneken, Guido	en_US
dc.date.accessioned	2014-12-08T15:36:21Z	-
dc.date.available	2014-12-08T15:36:21Z	-
dc.date.issued	2014-06-01	en_US
dc.identifier.issn	1530-4388	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/TDMR.2014.2320538	en_US
dc.identifier.uri	http://hdl.handle.net/11536/24689	-
dc.description.abstract	CDM ESD events can be a potential threat to SoC designs or heterogeneous 3D ICs with multiple power domains. Inter-layer ( or interface) circuits may need a local CDM ESD clamp that can prevent the unexpected failure under CDM ESD stress. In this letter, two local CDM ESD clamp circuits are proposed. They show better clamping efficiency under 2-ns vfTLP stress.	en_US
dc.language.iso	en_US	en_US
dc.subject	Electrostatic discharge (ESD)	en_US
dc.subject	charged device model (CDM)	en_US
dc.subject	cross-power domains ESD events	en_US
dc.subject	3D stacked ICs	en_US
dc.subject	vary-fast transmission line pulsing (vfTLP) systems	en_US
dc.title	Local CDM ESD Protection Circuits for Cross-Power Domains in 3D IC Applications	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/TDMR.2014.2320538	en_US
dc.identifier.journal	IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY	en_US
dc.citation.volume	14	en_US
dc.citation.issue	2	en_US
dc.citation.spage	781	en_US
dc.citation.epage	783	en_US
dc.contributor.department	交大名義發表	zh_TW
dc.contributor.department	National Chiao Tung University	en_US
dc.identifier.wosnumber	WOS:000337132200029	-
dc.citation.woscount	0	-
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