標題: | PushPull: Short-Path Padding for Timing Error Resilient Circuits |
作者: | Yang, Yu-Ming Jiang, Iris Hui-Ru Ho, Sung-Ting 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Delay padding;engineering change order;hold time fixing;linear programming;resilient circuits;timing analysis |
公開日期: | 1-四月-2014 |
摘要: | Modern IC designs are exposed to a wide range of dynamic variations. Traditionally, a conservative timing guardband is required to guarantee correct operations under the worst-case variation, thus leading to performance degradation. To remove the guardband, resilient circuits are proposed. However, the short-path padding (hold time fixing) problem in resilient circuits is far severer than conventional IC design. Therefore, in this paper, we focus on the short-path padding problem to enable the timing error detection and correction mechanism of resilient circuits. Unlike recent prior work adopts greedy heuristics with a local view, we determine the padding values and locations with a global view. Moreover, we utilize spare cells and a dummy metal to further achieve the derived padding values at physical implementation. Experimental results show that our method is promising to validate timing error-resilient circuits. |
URI: | http://dx.doi.org/10.1109/TCAD.2014.2304681 http://hdl.handle.net/11536/24744 |
ISSN: | 0278-0070 |
DOI: | 10.1109/TCAD.2014.2304681 |
期刊: | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS |
Volume: | 33 |
Issue: | 4 |
起始頁: | 558 |
結束頁: | 570 |
顯示於類別: | 期刊論文 |