完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lin, Yue-Min | en_US |
dc.contributor.author | Lin, Kun-Ping | en_US |
dc.contributor.author | Lee, Ting-Chi | en_US |
dc.contributor.author | Li, Meng-Ying | en_US |
dc.contributor.author | Lee, Chien-Ping | en_US |
dc.date.accessioned | 2014-12-08T15:36:33Z | - |
dc.date.available | 2014-12-08T15:36:33Z | - |
dc.date.issued | 2014-07-03 | en_US |
dc.identifier.issn | 0013-5194 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1049/el.2014.0629 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/24886 | - |
dc.description.abstract | An InAs-channel heterostructure field-effect transistor on GaAs substrates is presented. The conduction channel was formed by the InAs/AlAs0.16Sb0.84/AlSb quantum well. With the addition of the AlAs0.16Sb0.84 layer, holes that are generated by impact ionisation at high voltages are effectively confined in the InAs channel because of the large Delta Ev in this type-I heterostructure. By suppressing the hole injection into and accumulation in the buffer layer, the feedback through the back gate is eliminated and excellent output characteristics were obtained. The fabricated devices had a threshold voltage of about -0.6 V with a channel mobility of 18 100 cm(2)/V-s and a sheet carrier density of 1.2 x 10(12) cm(-2). | en_US |
dc.language.iso | en_US | en_US |
dc.title | InAs-based heterostructure field-effect transistor using AlAs0.16Sb0.84 double barriers | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1049/el.2014.0629 | en_US |
dc.identifier.journal | ELECTRONICS LETTERS | en_US |
dc.citation.volume | 50 | en_US |
dc.citation.issue | 14 | en_US |
dc.citation.spage | 1018 | en_US |
dc.citation.epage | U133 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
顯示於類別: | 期刊論文 |