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dc.contributor.authorLi, Yimingen_US
dc.date.accessioned2014-12-08T15:36:36Z-
dc.date.available2014-12-08T15:36:36Z-
dc.date.issued2006-12-01en_US
dc.identifier.issn1569-8025en_US
dc.identifier.urihttp://dx.doi.org/10.1007/s10825-006-0020-yen_US
dc.identifier.urihttp://hdl.handle.net/11536/24947-
dc.description.abstractIn this paper, electrical characteristics of 25 nm strained fin-typed field effect transistors (FinFETs) with oxide-nitride-stacked-capping layer are numerically studied. The FinFETs are fabricated on two different wafers, one is bulk silicon and the other is silicon-on-insulator (SOI) substrate. A three-dimensional device simulation is performed by solving a set of density-gradient-hydrodynamic equations to study device performance including, such as the drain current characteristics (the I-D-V-G and I-D-V-D curves), the drain-induced barrier height lowering, and the subthreshold swing. Comparison between the strained bulk and SOI FinFETs shows that the strained bulk FinFET is promising for emerging multiple-gate nanodevice era according to the manufacturability point of view.en_US
dc.language.isoen_USen_US
dc.subjectStrained bulk FinFETen_US
dc.subjectStrained SOI FinFETen_US
dc.subjectDevice simulationen_US
dc.subjectElectrical characteristicsen_US
dc.subjectDrain currenten_US
dc.subjectDrain-induced barrier height loweringen_US
dc.subjectSubthreshold swingen_US
dc.titleNumerical simulation and comparison of electrical characteristics between uniaxial strained bulk and SOI FinFETsen_US
dc.typeArticleen_US
dc.identifier.doi10.1007/s10825-006-0020-yen_US
dc.identifier.journalJOURNAL OF COMPUTATIONAL ELECTRONICSen_US
dc.citation.volume5en_US
dc.citation.issue4en_US
dc.citation.spage371en_US
dc.citation.epage376en_US
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.identifier.wosnumberWOS:000208997800024-
dc.citation.woscount1-
Appears in Collections:Articles