SUPPRESSION OF THE BORON PENETRATION INDUCED SI/SIO2 INTERFACE DEGRADATION BY USING A STACKED-AMORPHOUS-SILICON FILM AS THE GATE STRUCTURE FOR PMOSFET

標題:	SUPPRESSION OF THE BORON PENETRATION INDUCED SI/SIO2 INTERFACE DEGRADATION BY USING A STACKED-AMORPHOUS-SILICON FILM AS THE GATE STRUCTURE FOR PMOSFET
作者:	WU, SL LEE, CL LEI, TF CHEN, JF CHEN, LJ 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics
公開日期:	1-五月-1994
摘要:	This letter reports that the boron penetration through the thin gate oxide into the Si substrate does not only cause a large threshold voltage shift but also induces a large degradation in the Si/SiO2 interface. An atomically flat Si/SiO2 interface can be easily obtained by using a stacked-amorphous-silicon (SAS) film as the gate structure for p+ poly-Si gate MOS devices even the annealing temperature is as high as 1000-degrees-C.
URI:	http://dx.doi.org/10.1109/55.291600 http://hdl.handle.net/11536/2525
ISSN:	0741-3106
DOI:	10.1109/55.291600
期刊:	IEEE ELECTRON DEVICE LETTERS
Volume:	15
Issue:	5
起始頁:	160
結束頁:	162
顯示於類別：	期刊論文

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