標題: Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures
作者: Chen, Sau-Gee
Huang, Shen-Jui
Garrido, Mario
Jou, Shyh-Jye
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-Oct-2014
摘要: This paper presents a bit reversal circuit for continuous-flow parallel pipelined FFT processors. In addition to two flexible commutators, the circuit consists of two memory groups, where each group has P memory banks. For the consideration of achieving both low delay time and area complexity, a novel write/read scheduling mechanism is devised, so that FFT outputs can be stored in those memory banks in an optimized way. The proposed scheduling mechanism can write the current successively generated FFT output data samples to the locations without any delay right after they are successively released by the previous symbol. Therefore, total memory space of only N data samples is enough for continuous-flow FFT operations. Since read operation is not overlapped with write operation during the entire period, only single-port memory is required, which leads to great area reduction. The proposed bit-reversal circuit architecture can generate natural-order FFT output and support variable power-of-2 FFT lengths.
URI: http://dx.doi.org/10.1109/TCSI.2014.2327271
http://hdl.handle.net/11536/25361
ISSN: 1549-8328
DOI: 10.1109/TCSI.2014.2327271
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume: 61
Issue: 10
起始頁: 2869
結束頁: 2877
Appears in Collections:Articles