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dc.contributor.authorLi, YMen_US
dc.date.accessioned2014-12-08T15:37:07Z-
dc.date.available2014-12-08T15:37:07Z-
dc.date.issued2005en_US
dc.identifier.isbn3-540-29031-1en_US
dc.identifier.issn0302-9743en_US
dc.identifier.urihttp://hdl.handle.net/11536/25495-
dc.description.abstractIn this paper, parallel adaptive finite volume simulation of polysilicon thin-film transistor (TFT) is developed using dynamic domain partition algorithm on a PC-based Linux cluster with message passing interface libraries. A set of coupled semiconductor device equations together with a two-dimensional model of grain boundary for polysilicon TFT is formulated. For the numerical simulation of polysilicon TFT, our computational technique consists of the Gummel's decoupling method, an adaptive 1-irregular meshing technique, a finite volume approximation, a monotone iterative method, and an a posteriori error estimation method. Parallel dynamic domain decomposition of adaptive computing technique provides scalable flexibility to simulate polysilicon TFT devices with highly complicated geometry. This parallel approach fully exploits the inherent parallelism of the monotone iterative method. Implementation shows that a well-designed load balancing simulation significantly reduces the execution time up to an order of magnitude. Numerical results are presented to show good efficiency of the parallelization technique in terms of different computational benchmarks.en_US
dc.language.isoen_USen_US
dc.titleApplication of parallel adaptive computing technique to polysilicon thin-film transistor simulationen_US
dc.typeArticle; Proceedings Paperen_US
dc.identifier.journalHIGH PERFORMANCE COMPUTING AND COMMUNICATIONS, PROCEEDINGSen_US
dc.citation.volume3726en_US
dc.citation.spage829en_US
dc.citation.epage838en_US
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.identifier.wosnumberWOS:000233593200090-
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