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dc.contributor.authorWu, GMen_US
dc.contributor.authorChao, MCTen_US
dc.contributor.authorChang, YWen_US
dc.date.accessioned2014-12-08T15:37:16Z-
dc.date.available2014-12-08T15:37:16Z-
dc.date.issued2004-12-01en_US
dc.identifier.issn0167-9260en_US
dc.identifier.urihttp://dx.doi.org/10.1016/j.vlsi.2004.06.003en_US
dc.identifier.urihttp://hdl.handle.net/11536/25615-
dc.description.abstractImproving logic density by time-sharing, time-multiplexed FPGAs (TMFPGAs) have become an important research topic for reconfigurable computing. Due to the precedence and capacity constraints in TMFPGAs, the clustering and partitioning problems for TMFPGAs are different from the traditional ones. In this paper, we propose a two-phase hierarchical approach to solve the partitioning problem for TMFPGAs. With the precedence and capacity considerations for both phases, the first phase clusters nodes to reduce the problem size, and the second phase applies a probability-based iterative-improvement approach to minimize cut cost. Experimental results based on the Xilinx TMFPGA architecture show that our algorithm significantly outperforms previous works. (C) 2004 Elsevier B.V. All rights reserved.en_US
dc.language.isoen_USen_US
dc.subjectlayouten_US
dc.subjectphysical_designen_US
dc.subjectpartitioningen_US
dc.titleA clustering- and probability-based approach for time-multiplexed FPGA partitioningen_US
dc.typeArticleen_US
dc.identifier.doi10.1016/j.vlsi.2004.06.003en_US
dc.identifier.journalINTEGRATION-THE VLSI JOURNALen_US
dc.citation.volume38en_US
dc.citation.issue2en_US
dc.citation.spage245en_US
dc.citation.epage265en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000225661300005-
dc.citation.woscount0-
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