標題: | FPGA分割問題之研究 FPGA Partitioningzeng |
作者: | 黃界堅 HUANG, JIE JIAN 項春申 XIANG, CHUI KUN 電子研究所 |
關鍵字: | 用戶可程式邏輯閘陣列;分割;圖形分割;硬體模擬器;電子工程;FPGA;partition;graph partition;hardware emulator;ELECTRONIC-ENGINEERING |
公開日期: | 1994 |
摘要: | In this thesis, two important methods in Field Programming Gate Array (FPGA) partitioning for area minimization are investigated. The first method is the recursive Fiduccia- Mattheyses heuristic (RFM) which is a straightforward and fast method. This method uses the FM heuristic repeatedly to cut the input netlist. However, the result isn't good. An improvement scheme by repeatedly splitting and merging part of the input netlist is proposed. The cluster with the fewest gates is the seed for selecting other clusters. Then we merge selected clusters and repartition them. As compared with partitioning the whole netlist, the complexity of the problem is reduced, and as a result, the probability of getting better results is increased. Both RFM and the proposed scheme are implemented and tested by benchmarks from MCNC. As we expect, the experimental results show that the proposed scheme archives much improvement compare to RFM. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#NT834430007 http://hdl.handle.net/11536/59915 |
顯示於類別: | 畢業論文 |